1. Field of the Invention
The present invention relates to a surface mounted resin sealing type semiconductor device.
2. Related Background Art
In recent years, a smaller and thinner semiconductor device has been developed to make it commensurate with miniaturized and high-density electronic equipment. As a smaller and thinner resin sealing type semiconductor device, a semiconductor device called “Quad Flat Non-leaded Package (QFN)” or “Small Outline Non-leaded Package (SON)” in Which one side is sealed substantially is being developed. As a method for manufacturing, such a semiconductor device, in order to reduce an assembly cost, a method in which resin-sealing is conducted collectively with respect to at plurality of semiconductor devices, followed by dicing processing to divide into the individual semiconductor devices is becoming mainstream.
The following describes the semiconductor device disclosed in JP 11 (1999)-74440 A as a conventional example, with reference to FIGS. 15A to C. FIG. 15A is a plan view showing a schematic configuration of the conventional QFN type (SON type) resin sealing type semiconductor device, FIG. 15B is a cross-sectional view and FIG. 15C is a bottom view of the same. In this semiconductor device, an adhesive 3 is applied to a die pad 1 that is supported by a support lead 16, and a semiconductor element 2 is adhered thereon. On the periphery of the die pad 1, a plurality of electrode terminals 5 are disposed, and a top face of each electrode terminal 5 and the semiconductor element 2 are connected electrically with each other via a thin metal wiring 4.
The die pad 1, the semiconductor element 2, the adhesive 3, the thin metal wiring and the electrode terminals 5 are sealed with a sealing resin 7. The support lead 16 is subjected to bending so that the die pad 1 is embedded in the sealing resin 7. The sealing resin 7 is shaped in a quadrilateral flat plate form, and an under surface of the electrode terminal 5 on the reverse side of the surface connected with the semiconductor element 2 is exposed from a bottom face of the sealing resin 7. In addition, an end face of the electrode terminal 5 on the side of an outer edge of the sealing resin 7 is exposed from a side face of the sealing resin 7 continuously from the under surface exposed from the bottom face of the sealing resin 7. At the top of the electrode terminal 5, a groove 6 is formed. The groove 6 is formed so as to reduce the stress generated when dividing into the individual semiconductor devices from a lead frame (not illustrated) and to suppress the peeling between the electrode terminal 5 and the sealing resin 7 due to the stress generated before and after mounting the device into a board, whereby a break in the thin metal wiring 4 can be prevented.
The following describes the conventional example using a method of conducting resin-sealing with respect of a plurality of semiconductor devices and dividing it into the individual semiconductor devices by dicing processing in order to reduce an assembly cost, with reference to FIGS. 16A to C. This device is a conventional QFN type (SON type) resin sealing type semiconductor device. FIG. 16A is a plan view, FIG. 16B is a cross-sectional view and the FIG. 16C is a bottom view of the same. For simplifying the description, the same reference numerals are assigned to elements common to the above-described conventional example to describe them. In this semiconductor device, a support lead 9 is half etched at a rear face thereof so as to be embedded in a sealing resin 7. An end face of the electrode terminal 5 on the side of an outer edge of the sealing resin 7 is exposed from a side face of the sealing resin 7 discontinuously from an under surface exposed from a bottom face of the sealing resin 7. That is to say, as shown in FIG. 16B, a corner of the electrode terminal 5 located at a boundary between the bottom face and the outer end face of the sealing resin 7 is removed so as to form a discontinuously exposed state. As shown in FIG. 16C, for the purpose of making the semiconductor device thinner and enhancing the heat dissipation capability, a rear face of the die pad 1, which is on the opposite side from the semiconductor element-mounting surface, might be exposed from the sealing resin 7.
In these QFN type (SON type) semiconductor devices, one-side sealing is conducted so that the electrode terminals 5 are exposed from the bottom face of the sealing resin 7, which allows the semiconductor devices to be smaller and thinner.
However, in the configuration of the conventional semiconductor devices, the formation of the groove 6 on the electrode terminal 5 by etching causes the width of the groove to expand to an extent corresponding to the thickness of the lead frame. Therefore, the electrode terminal 5 is required to have a length sufficient to secure the groove width, so that there is a limit to shortening of the electrode terminal 5, thus making further miniaturization of the semiconductor device difficult.
Additionally, when a method of conducting the resin-sealing collectively with respect of a plurality of semiconductor devices and dividing it into the individual semiconductor devices by dicing processing is employed in order to reduce an assembly cost, the dicing processing causes metal burrs on the electrode terminal 5. Since these burrs lead to a problem when packaging the device into a board, the corner of the electrode terminal 5 has to be removed so that the electrode terminal 5 is exposed discontinuously from the under surface to the end face, which means that the corner of the electrode terminal 5 is not exposed from the outer edge of the bottom face of the sealing resin 7 as shown in FIGS. 16B and C. In this case, an outer edge portion of the electrode terminal 5 has to be half-etched to be embedded into the sealing resin 7, thus making it quite difficult to shorten the electrode terminal 5.